This Summary is provided to introduce in a simplified form a selection of concepts that are further described below in the Detailed Description. This Summary is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to limit the scope of the claimed subject matter.
A magnetic random access memory (MRAM) array is disclosed. The MRAM array may include a plurality of memory data bit line groups configured to store data, a plurality of reference bit lines configured to provide a reference voltage, wherein the reference voltage is based on voltages provided by at least one resistive bit cell of each reference bit line, and a plurality of sense amps configured to compare a data bit line voltage from the plurality of memory data bit line groups to the reference voltage.
In another example, a voltage generator to provide a reference voltage is disclosed. The reference voltage generator may include a plurality of resistive bit cells configured to store a first logic state and a second logic state, wherein a reference voltage is provided based on a first number of resistive bit cells storing the first logic state and a second number of resistive bit cells storing the second logic state.
In another example, a magnetic random access memory (MRAM) array may include a means for storing data via a plurality of memory data bit line groups, a means for providing a reference voltage based on voltages provided by at least one resistive bit cell, and a means for comparing a data bit line voltage from the plurality of memory data bit line groups to the reference voltage.